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W9825G6JH
5. PIN DESCRIPTION
PIN NUMBER
23 ? 26, 22,
29 ? 36
20, 21
PIN NAME
A0 ? A12
BS0, BS1
FUNCTION
Address
Bank Select
DESCRIPTION
A0 ? A8Multiplexed pins for row and column address.
Row address: A0 ? A12. Column address: A0 ? A8.
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
DQ0 ? DQ15
Data
Input/Output
Multiplexed pins for data output and input.
51, 53
Disable or enable the command decoder. When
19
CS
Chip Select
command decoder is disabled, new command is
ignored and previous operation continues.
18
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of
the clock, RAS , CAS and WE define the
operation to be executed.
Column
17
CAS
Address
Referred to RAS
Strobe
16
WE
Write Enable Referred to RAS
The output buffer is placed at Hi-Z(with latency of 2)
15, 39
LDQM,
UDQM
Input/Output
Mask
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
38
CLK
Clock Inputs
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
37
1, 14, 27
CKE
V DD
Clock Enable When CKE is low, Power Down mode, Suspend mode,
or Self Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
28, 41, 54
V SS
Ground
Ground for input buffers and logic circuit inside DRAM.
3, 9, 43, 49
6, 12, 46, 52
40
V DDQ
V SSQ
NC
Power (+3.3V) Separated power from V DD , to improve DQ noise
for I/O Buffer immunity.
Ground Separated ground from V SS , to improve DQ noise
for I/O Buffer immunity.
No Connection No connection.
Publication Release Date: Mar. 13, 2014
-6-
Revision: A09
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